#include <iom128.h>
#include <inavr.h>

#include "config.h"
#include "bitop.h"
#include "uart.h"
#include "opcmd.h"
#include "1wslave.h"
#include "led.h"

#define TRUE    1
#define FALSE   0

#define FULL	1
#define EMPTY	0

#define INPUT  1
#define OUTPUT 0

#define DQ_BIT   BIT1
#define DQ_OUT  PORTD
#define DQ_DDR  DDRD
#define DQ_IN   PIND

#define dq_to_input     bit_clear(DQ_DDR,DQ_BIT)
#define dq_to_output    bit_set(DQ_DDR,DQ_BIT)
#define dq_w_high       bit_set(DQ_OUT,DQ_BIT)
#define dq_w_low        bit_clear(DQ_OUT,DQ_BIT)
#define dq_r            bit_get(DQ_IN ,DQ_BIT)


#define M_R_C				0x01		 
#define M_F_C				0x02    	


#define INIT_SEQ		  ( flaga_Tx=0, flaga_Rx=0, flaga_BUF_Rx=0, \
		flaga_busy=0, flaga_Match_ROM=0, licznik_bit=0, \
		status=0x00 )



//-----------------------------------------------------------

volatile unsigned char 	flaga_Rx, flaga_Tx;			
volatile unsigned char	flaga_BUF_Rx;					
unsigned char	flaga_Match_ROM;
unsigned char 	flaga_busy;						
unsigned char	status;							
// i w Function Commands Flow

unsigned char 	BUF_Rx;							
unsigned char	bRx;								
//unsigned char 	BUF_Tx[(2+SENSOR_MAXCNT_PER_GPIO)*GPIO_PINS_IN_USE];	
unsigned char 	BUF_Tx[32];	
unsigned short	max_index_buf;					
unsigned char 	SN[8];							

unsigned char   licznik_bit;					
unsigned short  index_buf;						
unsigned char   del_count;						



void w1s_init(void)
{
	INIT_SEQ;
	BUF_Rx = 0;

	bit_set(DQ_OUT,DQ_BIT);
	bit_clear(DQ_DDR,DQ_BIT);   //set pin portd.1 input
	delayms(100);

	EICRA |= 0x08;
	EIMSK |= 0x02;


}

#if 1
#pragma vector=INT1_vect
__interrupt  void Int1_Isr(void)
	//---------------------------------------------------------------------------
{
#if(UART_DEBUG)
	u08 err = 0;
#endif
	led_on();


	bit_clear(EIMSK,BIT1); 

	if (flaga_Tx)
	{
		//F(("$ %x",BUF_Tx[0]));
		if (BUF_Tx[index_buf] & 0x01)
		{
			dq_w_high;
			dq_to_output;
			delayus(20);
			dq_to_input;
		}
		else
		{
			dq_to_output;
			dq_w_low;
			delayus(20);
			dq_w_high;
			delayus(10);
			dq_to_input;
		}
		BUF_Tx[index_buf] >>= 1;	

		if (++licznik_bit == 8)
		{
			if (flaga_busy)     		
				index_buf = 0;			
			else if (++index_buf == max_index_buf)
			{
				INIT_SEQ;
				//F(("@"));
			}

			licznik_bit = 0;
		}
		if (dq_r)
		{
			bit_set(EIFR,BIT1);
			bit_set(EIMSK,BIT1);
			led_off();
			return;
		}
		else
		{
			del_count = 45;			
			while (del_count--)
			{
				if (dq_r)
				{
					bit_set(EIFR,BIT1);
					bit_set(EIMSK,BIT1);
					led_off();

					return;
				}
			}
#if(UART_DEBUG)
			err = 2;
#endif
			goto RST;
		}
	}
	if (flaga_Rx)
	{
		//F(("^"));
		delayus(15);
		bRx = dq_r;

		flaga_BUF_Rx = EMPTY;			
		if (++licznik_bit == 8)
		{
			//F(("&&\r\n"));
			flaga_BUF_Rx = FULL;		
			index_buf++;
			licznik_bit = 0;
		}

		BUF_Rx >>= 1;
		if (bRx)
			BUF_Rx |= 0x80;

		delayus(5);
		if (dq_r)
		{
			led_off();
			bit_set(EIFR,BIT1);
			bit_set(EIMSK,BIT1);
			return;						
		}
		else
		{
			del_count = 50;			
			while (del_count--)		
			{
				if (dq_r)
				{
					led_off();
					bit_set(EIFR,BIT1);
					bit_set(EIMSK,BIT1);
					return;				
				}
			}
			// goto RST;				
			//F(("##\r\n"));
#if(UART_DEBUG)
			err = 1;
#endif
		}

	} 

	//---------------------------------------------------------------------------
RST :
	delayus(200); 
	while(dq_r == 0);
	delayus(10);
	dq_to_output;
	dq_w_low;
	delayus(200);
	{
		INIT_SEQ;
		flaga_Rx = TRUE;
		status 	= M_R_C;
	}

	dq_to_input;
	dq_w_high;

	led_off();
	bit_set(EIFR,BIT1);
	bit_set(EIMSK,BIT1);
	F(("reset[%x]!\r\n",err));
	return;
}
#endif 

#define CMD_LEN       3
//#define CMD_LEN2       11
//#define CMD_RET_LEN   ((2+SENSOR_MAXCNT_PER_GPIO)*GPIO_PINS_IN_USE)
#define CMD_RET_LEN   32

static unsigned char m_cmd[CMD_LEN+1] = {0};
static unsigned char m_cmd_idx = 0;
static unsigned char m_cmd_ret[CMD_RET_LEN];


unsigned long aa=0;
extern u08*	g_buff_handle_master;
void w1s_wait_cmd(void)
{
	//unsigned short i;
	//unsigned short len =0 ;
	u16 i;
	u16 len = 0;
	s16 ret;

	__clear_watchdog_timer();

	if (flaga_BUF_Rx == FULL)			
	{
		bit_clear(EIMSK,BIT1);//disable master interrupt

		flaga_BUF_Rx = EMPTY;

		m_cmd[m_cmd_idx]=BUF_Rx; 

		m_cmd_idx=(m_cmd_idx+1)%CMD_LEN;

		if(!m_cmd_idx) //get one cmd
		{
			F(("cmd_recv:[%x][%x][%x]\r\n",m_cmd[0],m_cmd[1],m_cmd[2])); 

			ret = handle_master_cmd(m_cmd,g_buff_handle_master,&len);

			F(("cmd_ret: %d len= %x\r\n",ret,len));  

			for(i=0; i<len; i++)
			{
				BUF_Tx[i] = m_cmd_ret[i];
				__clear_watchdog_timer();
				//F(("%x ",m_cmd_ret[i]));
			}
			//F(("\r\n\r\n"));
			flaga_Rx = FALSE;
			index_buf = 0;
			max_index_buf = len;	
			flaga_Tx = TRUE;               
		} 
		bit_set(EIMSK,BIT1);//enable master interrupt 
	}
}
